Field of the Invention
The invention relates to a method for testing integrated semiconductor memory devices, in particular DRAM memories, or the like.
In order to obtain economic yields, in integrated semiconductor memory devices it is necessary to provide repair memory blocks with corresponding repair memory cells or replacement memory cells.
These memory cells of the repair memory blocks are intended to replace defective memory cells that occur. To that end, for each memory module, in particular for each DRAM module or the like, it is necessary to determine a corresponding replacement scheme, redundancy scheme or repair scheme. In order to determine such a replacement scheme, specific tests are carried out on the integrated semiconductor memory device, that is to say in particular on the DRAM memory or the like.
In prior-art methods for testing integrated semiconductor memory devices, in particular DRAM memories, or the like, at least one test is carried out on a memory area of the semiconductor memory device. Test result data for the memory area are generated for each test carried out and/or during each test carried out. For evaluation purposes and/or for further process steps, the test result data of the memory area are buffer-stored externally at least temporarily after a respective test carried out, outside the semiconductor memory device to be tested.
These known methods for testing integrated semiconductor memory devices are disadvantageous to the effect that as the memory size continually increases, that is to say with increasing integration density of the semiconductor memory devices, the bandwidth present for data exchange does not suffice, with regard to the outputting of the test result data, for keeping brief the respective transmission times for the transfer of the result data. Moreover, the respective bandwidth in the transmission channel cannot be increased in a straightforward manner.
It is accordingly an object of the invention to provide a method for testing integrated semiconductor memory devices that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that tests integrated semiconductor memory devices, in which the time taken for the transmission of the test result data is particularly short.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for testing integrated semiconductor memory devices, in particular DRAM memories or the like, is characterized in that the test result data of the memory area of the semiconductor memory device are in each case formed, transmitted, and/or stored as a plurality of blockwise test result lists.
Consequently, it is a basic idea of the present invention not to carry out the organization and the transmission of the test result data in a single data block that corresponded precisely to the entire memory area, but rather to carry out the data organization and transmission in a blockwise manner in the form of so-called test result lists. This has the advantage that only the quantity of data representative of a respective block ever arises at a specific point in time and, consequently, the memory and management outlay arises in a temporally apportioned manner. As a result of the method, circuitry necessities such as area-intensive memory circuits or the like can be obviated or reduced. As a result of which, the previous channel bandwidths also remain adequate for data transmission.
Although this procedure is already advantageous when forming a test scheme with only a single test, the procedure according to the invention is appropriate precisely when carrying out a plurality of tests, in particular in a successive manner.
In this case, it is particularly advantageous if each of the tests to be carried out is carried out in a blockwise manner in each case in the memory area. This means that in each case only one area of the overall memory area that is provided and is to be tested is ever tested and that also, as a result, only test result data with regard to this respectively tested block ever arise and have to be managed and transmitted.
Although this is not mandatory, it is preferable for the same block structure to be used as a basis for the blockwise assignment of the test result data to the test result lists and/or the execution of the test.
In this case, it is furthermore preferable for in each case a block structure to be used as a basis that corresponds to that block structure of a blockwise configuration, interconnection, and/or organization of the memory area of the semiconductor memory device in a plurality of memory blocks, in particular in matrix form in each case.
The blockwise test result lists, which may be formed in particular in matrix form, may be formed, transmitted, and/or stored in each case after a specific number or after specific numbers of tests carried out. This is advantageously done after each individual test carried out. This makes it possible, in a particularly advantageous manner, to track the defect evolution of the entire memory area for the individual tests.
The test result lists are configured particularly clearly if they are formed as accumulated blockwise defect lists, in particular as accumulated blockwise defect matrixes or the like, in particular as so-called fail maps or the like.
In this case, the term accumulating or accumulation is to be understood to mean, in particular, the so-called xe2x80x9csummationxe2x80x9d of defects over a span of tests that are to be executed one after the other. In this case, the accumulated defect list or fail map specifies, after a test Tj which is intended to be the jth test in the series of all the tests, which memory cells of the respective block of the memory area have exhibited at least one defect in the previous j tests carried out. If appropriate, the term accumulation can also be understood to the effect that, for each cell of a respective block of the memory area, it is recorded whether and what defect it has exhibited for each of the j tests previously carried out, even though this detailed information will not generally be necessary.
It is particularly preferred that in each case a blockwise accumulated defect list is formed, transmitted and/or stored externally for each individual test carried out and after each test carried out, so that, in particular after carrying out all the tests on all the blocks, accumulating or accumulated defect lists for all the individual tests carried out are present for each of the tested blocks.
The test result list may be accumulated outside the area of the semiconductor memory device, that is to say externally, in particular in an external test device that is provided, if appropriate.
However, it is particularly preferred that the test result lists are accumulated within the area of the semiconductor memory device. In this case, it is then provided that, for each block individually in each case, firstly the respective blockwise accumulated defect list from a previous group of tests carried out or a previously carried out individual test for the respective block is externally transmitted and/or read into the semiconductor memory device, in particular from the external test device that is provided, if appropriate, the test result data or test result lists of the group of tests currently being carried out or of the test currently being carried out for the respective block are accumulated to form a current blockwise accumulated defect list for the respective block, and the respective current blockwise accumulated defect list for the respective block is then transmitted to a point outside the semiconductor memory device and/or stored, in particular in the area of the external test device that is provided, if appropriate.
In order to further shorten the times for transferring the test result lists or test result data, it is provided that the test result lists and, in particular, the accumulated defect lists, for example the defect matrixes or the like, are formed, transmitted, and/or stored in compressed fashion.
Preferably, the test results lists are compressed. In particular, the accumulated defect lists are compressed. In this case, most cell addresses of memory cells of a memory block that are defective during at least one test are taken up in a respective test result list. Furthermore, the cell addresses are preferably placed in the respective accumulated defect list as individual defects.
Furthermore, in the case of memory blocks configured in a matrix-like manner in columns and rows, column addresses and/or row addresses are used as cell addresses for specifying individual defects in the test result lists. These cell addresses can identify individual defects in the accumulated defect lists.
It has been shown that when specific numbers of defective memory cells occur in an area of a memory block of the memory area, individual defect correction is no longer expedient. In particular, the memory areas are often constructed and formed in a matrix-like manner. In these matrix-like memory areas with corresponding columns and rows, specific defects cause entire columns and/or entire rows of memory cells of a memory block of the memory area to fail or be defective, so that they would have to be replaced in their entirety.
Accordingly, it is particularly advantageous if, when a maximum number of defects is exceeded in a column or a row of a respective memory block of the memory area, this column or row, is taken up as a so-called must repair into the test result list and, in particular, into the accumulated defect list. This is done in particular by a must repair being specified by exclusive specification of the defective column or row, cell addresses of possible individual defects in the respective column or row that had already been noted beforehand and/or are to be noted later being removed from the test result list and, in particular, accumulated defect list or not being taken up therein.
In order to repair defective memory areas, provision is made of corresponding replacement memory blocksxe2x80x94often also blockwise. These blocks may, of course, likewise be defective. Therefore, it is preferred that possibly provided replacement/repair memory blocks are concomitantly taken into account and accordingly concomitantly tested during the division and/or assignment of the memory blocks and/or of the test result lists and accumulated defect lists.
In accordance with a preferred embodiment of the method, the tests may be formed, compiled, carried out, and/or evaluated essentially in the area of the semiconductor memory device, that is to say on-chip. It is particularly advantageous, however, if the tests are formed, compiled, carried out, and/or evaluated essentially in an area outside the semiconductor memory device, in particular in the area of an external test device that is provided, if appropriate. In this case, specially designed automatic testers, for example in the form of PC plug-in cards, may be provided and the respective memory chip affords more space for the actual memory area.
It is furthermore provided that on the basis of the test result lists and, in particular, of the accumulated defect lists, redundancy, repair and/or replacement schemes are generated, in particular for the replacement of defective individual cells, entire columns and/or rows by optionally provided repair/replacement memory blocks or parts thereof.
These redundancy, repair and/or replacement schemes are often carried out after the test cycle which takes place in a pre-fused stage of production. This is then often embodied in final form by a so-called fusing process, in which the replacement scheme and the associated circuit layout are permanently burned into the memory chip. In a post-fusing step, the memory module is then finally tested and then, because it can no longer be corrected or repaired, rejected in the event of just a single defect occurring.
It is economically expedient, therefore, in accordance with a particularly preferred embodiment of the method according to the invention, that the redundancy, repair, and/or replacement schemes are generated and/or executed incrementally, in particular after specific groups of tests carried out and/or after individual tests carried out.
In this case, it is furthermore advantageous that after each incremental redundancy, repair and/or replacement scheme that has been generated and/or carried out, previous tests or groups thereof are carried out anew in the memory area in a blockwise manner, in particular in order to assess the quality and the result of the correction carried out on the basis of the redundancy, repair and/or replacement scheme respectively employed.
This measure may be taken in addition to the measure that after each incremental redundancy, repair and/or replacement scheme that has been generated and/or carried out, the method continues with subsequent tests or groups thereof in the memory area.
In accordance with a further embodiment of the method according to the invention, it is provided that the redundancy, repair and/or replacement schemes are initially executed provisionally, in particular in a pre-fusing phase of the fabrication of the semiconductor memory device.
The formation and/or carrying out of incremental replacement schemes also enables the further data reduction in the case of the accumulated defect lists. Thus, it is conceivable, if the correct configuration of a replacement scheme that has been generated and/or carried out has been shown, to reset the respective defect list of a memory block of the memory area to zero, so that henceforth only newly arising defects are tracked in the accumulating defect list. However, this procedure is not mandatory but rather exclusively represents a further alternative of the procedure according to the invention.
In an advantageous manner, the formation, the compilation, the if appropriate also provisional carrying out and/or the testing of the redundancy, repair and/or replacement schemes is effected essentially in the area of the semiconductor memory device, that is to say on-chip.
As an alternative to this, the formation, the compilation, the if appropriate also provisional carrying out and/or the testing of the redundancy repair and/or replacement schemes may also be carried out in the area of an external test device that is provided.
The subject matter of the invention and its advantages over the prior art are elucidated further below through the following explanations.
In order to obtain economic yields, in DRAM modules it is necessary to provide repair cells which can replace defective memory cells. To that end, for each chip, it is necessary to determine a replacement scheme that is generally calculated by an external memory tester (ATE: Automatic Test Equipment). For the calculation, for each test step, the defect information must be read from the chip into the ATE.
On account of the known development that the memory size increases from year to year to a significantly greater extent than the bandwidth on the channel between chip and ATE, it turns out that the transmission time for the defect transfer is increasingly becoming a cost factor.
There are now proposals for compressing the defect information to a great extent in that, instead of the pass/fail information per cell, only the defect addresses and/or, in the event of a specific number of defects being exceeded per word or bit line, the corresponding line is identified as non-repairable.
Further-reaching proposals provide for the replacement scheme to be completely calculated on the chip. In this case, the problem quickly arises thatxe2x80x94even with high compressionxe2x80x94the information to be stored on the chip demands too much chip area. It is possible, then, to limit the test to relatively small blocks in which the replacement is calculated separately in each case. However, this leads to a considerable lengthening of the test time, since the test-inherent waiting times arise sequentially for all the blocks.
The present invention provides for two aims to be achieved simultaneously by blockwise transmission of, if appropriate, suitably compressed defect matrixes: (a) carrying out the tests using testers of low bandwidth at very high speed with no loss of defect information and (b) relocation of the area-intensive circuits (depending on concept buffer memory, redundancy processor) to an external tester.
Advantages of the invention described are the following:
reduction of the area requirement for BISR (Built-in-self-repair),
very high data compression for the transmission of the defect information,
possibility of using very inexpensive external testers (e.g. PC with plug-in card), and
possibility of using highly efficient algorithms of external testers.
One particular idea is the approach that the defect information to be accumulated can be transferred in a blockwise manner between the chip and external memory. In particular, the possibility of loading the defect information for a memory block from the external tester back into the chip again is also covered.
Inter alia, the following embodiments of the method according to the invention are produced:
a) Accumulation of the Defect Information and External Redundancy Calculation.
The buffer memory for the defect addresses of a block and a logic configuration for taking up new defects into the buffer memory are situated on the chip. Use is made of the requirement that at most a maximum of NRBL/NRWL defect addresses are to occur per word or bit line. If more defects are found, the respective line must be completely replaced; it then suffices to store the address of the corresponding word or bit line or row or column, respectively.
For each read operation, the procedure is as follows: for each block:
1) the defect information is transferred from the ATE to the chip,
2) the read operation is executed, the added defects being accumulated on-chip, and
3) the defect information on-chip, which now contains the defects in this block cumulated for all the tests that have taken place beforehand, is transferred back to the ATE.
After the conclusion of all the tests, the cumulated defect information is present for each block in the ATE. The redundancy processor of the ATE can then distribute the remaining individual cell defects between the remaining repair lines.
b) Connection to On-chip Test Pattern Generator and External Buffer Memory.
If the test pattern generation is effected on-chip, it would be advantageous for a buffer memory to be available externally per chip. The buffer memory can be independently written to and read from by the chip. The buffer memory could be applied e.g. directly on the needle card. Instead of the ATE, only a simple test sequence control would then be necessary which prescribes the order of the tests and reads out the end result. The ultimate redundancy calculation could then be implemented on-chip, together with the buffer memory or in the external ATE.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for testing integrated semiconductor memory devices, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.